The present invention relates to a technique for fabricating a semiconductor integrated circuit device; and, more particularly, the invention relates to a technique which is effective in its application to a wafer testing step, including a probe check.
According to studies made by the present inventor in connection with the fabrication of a semiconductor integrated circuit device, for example, it has been found that Japanese Unexamined Patent Publication Nos. Hei 5(1993)-343497 and 5(1993)-136219 disclose techniques associated with a wafer testing step, including a probe check.
For example, in the former publication No. Hei 5(1993)-343497, there is disclosed wafer inspection equipment provided with plural wafer inspection units and a cassette stock unit, wherein wafers stored in a predetermined cassette, out of plural cassettes stocked in the cassette stock unit, are taken out one by one from the cassette and conveyed for inspection to the plural wafer inspection units, respectively, by wafer conveyance means, and then they are conveyed successively, beginning with one that has been checked in any of the wafer inspection units, to the original cassette and are received therein.
In the latter publication No. Hei 5(1993)-136219, there is disclosed inspection equipment provided with plural inspection mechanisms and a probe card conveying mechanism, wherein inspection is carried out under successive loading and unloading of wafers with respect to the plural inspection mechanisms, and a predetermined probe card is conveyed and automatically loaded to each inspection mechanism by the probe card conveying mechanism in accordance with the type of wafer, thereby allowing inspection to be carried out.